The price paid for this stability is two additional parts, slightly increased dropout voltage, and the dissipation introduced by Rseries. Another benefit is immunity to instability caused by ceramic load capacitance that can destabilize the circuit of Figure 3. In contrast, Rseries in Figure 4 is known and stable making it easy to place the zero created by Rseries and Cout at a frequency of choice. The ESRcout in Figure 3 is seldom known accurately, has no guaranteed value or range, and can vary > 2:1 with temperature. By inspection one can see that if Rseries is equal to ESRcout and Cff is large enough to “short out” Rfb1 at frequencies of interest, then from a stability point of view we have similar circuits - but with a major exception. Figure 4 shows the same regulator but a series resistor and a feed forward capacitor have been added and the Cout has no ESR. ![]() It requires a small capacitor, a resistor, and access to the feedback pin making it applicable to adjustable regulators.įigure 3 shows a typical LDO regulator configuration with Cout and its required internal ESR. This design idea presents a simple method to stabilize voltage regulators that were not designed to be stable with ceramic output capacitors. Adding more capacitance in search of a cure may instead make the instability even more pronounced but at a reduced frequency. When one tries to use a regulator of this design type with a Cout having very low ESR he will often see an oscillation at a frequency >50 kHz or prolonged ringing following transients due to low phase margin in the feedback loop. The zero is provided by Cout and its ESR. Like the LDO, this compensation scheme requires a second zero to be placed below the loop's unity gain frequency to provide >45degrees phase margin. Many voltage mode switching ICs use a high DC gain GM error amplifier with an internal pole set at low frequency and an internal zero set near the expected LC output double pole location. Figure 2 shows an example Bode plot with 2 poles and a zero placed to provide a stable design.įigure 1: LDO with control loop and high DC gain This zero must be placed below the loop's unity gain frequency to provide >45degrees phase margin. These device types generally rely on the zero formed by Cout and its ESR to cancel one pole to provide adequate phase margin and a stable loop. A second pole is formed by Cout in parallel with the load resistance. Low dropout linear regulators (LDOs) that use a PNP or PFET pass element have control loops with high DC gain and one internal low frequency pole as illustrated in the simplified schematic of Figure 1. ![]() So, why do many switcher and LDO linear regulator datasheets stipulate tantalum caps and warn that ceramic caps are inappropriate? The answer is feedback loop stability. They provide wide operating temperature range, small footprint, high ripple current capacity, high surge current, very low ESR, over-voltage tolerance, long life, and reasonably low cost. Ceramic capacitor characteristics make them nearly ideal for use in power supplies.
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